Questions about memory-barriers
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why does read barrier can causes all effects prior to storage from another cpu be perceptible?
Documentation about memory barriers of linux kernel(https://www.kernel.org/doc/Documentation/memory-barriers.txt) has this example to illustrate the read barrier in the SMP case can be used to causes ...
AndrewHan
Votes: 0
Answers: 0
What's the relationship between CPU Out-of-order execution and memory order?
In my understanding, CPU changes the operations order which are written on machine code for optimization and it is called out-of-order execution.
In the term "memory order", it defines the o...
hidetatz
Votes: 0
Answers: 1
Synchronizing caches for JIT/self-modifying code on ARM
The general, more abstract procedure for writing and later executing JIT or self-modifying code is, to my understanding, something like the following.
Write the generated code,
make sure it's flushed...
Mona the Monad
Votes: 0
Answers: 1
Can atomic_thread_fence(acquire) prevent previous loads being reordered after itself?
I understand atomic_thread_fence in C++ is quite different with atomic store/loads, and it is not a good practice to understand them by trying to interpret them into CPU(maybe x86)'s mfence/lfence/sfe...
calvin
Votes: 0
Answers: 1