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Questions - verilog

Constrain total number of array elements less than predetermined value

I'm trying to create an array with a constraint on the total number of array elements less than given value. For example, I want to generate a random array where the total number of elements less than...
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mdems

random

constraints

verilog

system-verilog

Votes: 0

Answers: 2

Latest Answer

Calling a user defined function in a constraint creates problems because the values for the input argument (in this case abs_vals) get picked before calling the function, and the output of the functio...
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dave_59

Clarification on uses of posedge in "if"

I'm trying my hand at teaching myself some Verilog. I'm trying to make a mod-10 counter that iterates every second or so. The code I'm trying to modify is some I found on an old forum. I've tried to u...
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Tesla047

verilog

Votes: 0

Answers: 1

Latest Answer

You get the syntax error because the usage of the posedge keyword is illegal in the following line: if (posedge counter[26]) begin It is illegal because there is no timing event control. For ex...
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toolic

Modulating a signal on-off at 10kHz

I have written the code for the input clk = 10MHz and output_clk = 5MHz. I want to modulate the output_clk on-off at 10kHz as shown in the example signal. But, my current code only modifies the output...
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Pressing_Keys_24_7

verilog

Votes: 0

Answers: 1

Latest Answer

You can create a new signal which follows mclk1 but is gated by the 10kHz signal: wire mclk1gated = mdata1 ? mclk1 : 0; Here is a complete code example: module tb; bit mclk1,mdata1; // mclk1 = 10M...
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toolic

Verilog - Assign an output that lasts more than 1 clock cycle

I have designed a simple sequence detector that works, but I am wondering how I can edit it so that the valid_password outputs as high for 3 clock cycles regardless of input changes. Here is what I've...
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NotAProgrammer

verilog

vivado

Votes: 0

Answers: 1

Latest Answer

Try a delay register. Here trigger register will assert high when valid_password condition hits. This is then passed on for two cycles. reg [2:0] trigger; always@(posedge clk or negedge rstn) begin ...
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Pradyuman Bissa

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