python (12.9k questions)

javascript (9.2k questions)

reactjs (4.7k questions)

java (4.2k questions)

java (4.2k questions)

c# (3.5k questions)

c# (3.5k questions)

html (3.3k questions)

Questions - system-verilog

Constrain total number of array elements less than predetermined value

I'm trying to create an array with a constraint on the total number of array elements less than given value. For example, I want to generate a random array where the total number of elements less than...
test-img

mdems

random

constraints

verilog

system-verilog

Votes: 0

Answers: 2

Latest Answer

Calling a user defined function in a constraint creates problems because the values for the input argument (in this case abs_vals) get picked before calling the function, and the output of the functio...
test-img

dave_59

Does Verilator support SystemVerilog libraries?

When compiling RTL from multiple sources it is normal to compile them into separate SystemVerilog libraries. Doing this means they cannot interfere with each other, and you can compile multiple diffe...
test-img

WestHamster

system-verilog

verilator

Votes: 0

Answers: 1

Latest Answer

No and it never will. Chapter 33 of the LRM is specifically procluded from being supported by Verilator. See here: https://github.com/verilator/verilator/blob/master/docs/internals.rst#never-features...
test-img

WestHamster

Can you import a vhdl package in a systemverilog file?

Can you import a vhdl package in a systemverilog file? Let's say I have a VHDL package: library ieee; use ieee.std_logic_1164.all; -- FILE: my_pkg.vhd package my_pkg is type ty...
test-img

pico

vhdl

system-verilog

Votes: 0

Answers: 2

Latest Answer

I am only aware of one tool, Modelsim/Questa that allows sharing of packages between SystemVerilog and VHDL, and only for the sharing of data types/typedefs across these languages. The most useful pu...
test-img

dave_59

Are SystemVerilog packed arrays row or column major for literal assignment?

I want to use multi-dimensional arrays for some SystemVerilog code that I intend to synthesize. My understanding is that packed arrays are essentially a big vector that can be indexed slice or element...
test-img

darsnack

arrays

system-verilog

synthesis

Votes: 0

Answers: 1

Latest Answer

There are a couple of problems with your code. The use of the single number range [2] is not allowed and the 1800-2023 LRM will be more explicit about why this is not allowed. Some tools have allowed ...
test-img

dave_59

Posts

Questions

Blogs

Jobs