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Questions - vhdl

Need help to figure out syntax error code

I've been following a few snippits given by professor to fill in gaps of code and now that I am finished I'm get and I keep getting error and can't figure out what its asking Error (10500): VHDL synta...
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Ben G

syntax-error

vhdl

Votes: 0

Answers: 1

Latest Answer

when is only supported inside a process when the VHDL standard is set to 2008 or later. In your code example, there is no need for a process and the assignment to D can be done without the process.
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Tricky

Can you import a vhdl package in a systemverilog file?

Can you import a vhdl package in a systemverilog file? Let's say I have a VHDL package: library ieee; use ieee.std_logic_1164.all; -- FILE: my_pkg.vhd package my_pkg is type ty...
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pico

vhdl

system-verilog

Votes: 0

Answers: 2

Latest Answer

I am only aware of one tool, Modelsim/Questa that allows sharing of packages between SystemVerilog and VHDL, and only for the sharing of data types/typedefs across these languages. The most useful pu...
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dave_59

VHDL Increment Signal doesn't work properly

I have a problem with my vhdl code. I have a signal whitch I want to increment every phase. So i wrote this code: --module.vhd enter image description here library ieee; use ieee.std_logic_1164.all;...
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patro98

vhdl

Votes: 0

Answers: 2

Latest Answer

Your code is syntactically correct, and will increment Q_int by the required amount. The problem is that Q_int is initialised to "UUUU" and is not assigned a value on reset. And when you add...
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Tricky

VHDL ERROR: formal port 'num' has no actual or default value

I have this compilation error in Vivado when trying to port a simple testing device to setup simulations. This is found when standing on the 'uut : testing_logic' line. I have triple checked my commas...
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Anthony DeVore

port

vhdl

Votes: 0

Answers: 1

Latest Answer

To your problem is just that you don't use the proper syntax for port mapping your this is the correct syntax uut : testing_logic port map( num =>num_TB, btn_add => btn_a...
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Ali Redha

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