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Questions - arinc

Different Clock Domain VHDL

I'm making a custom hardware ARINC 429 Core. For now I have described the module in transmission (TX-FSM), according to the ARINC 429 standard and a FIFO in transmission from which it takes the data a...
test-img

KemKing

vhdl

hdl

fsm

arinc

Votes: 0

Answers: 1

Latest Answer

Run both FIFOs at the 2 MHz clk2M, and then generate a single cycle enable indication on TX_FIFO_rd when FIFO read data transfer is required. Thereby you can get the benefit from synchronous design, w...
test-img

Morten Zilmer

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