python (12.9k questions)

javascript (9.2k questions)

reactjs (4.7k questions)

java (4.2k questions)

java (4.2k questions)

c# (3.5k questions)

c# (3.5k questions)

html (3.3k questions)

Questions - hdl

Why this process is executed when the simulation starts

This is a simple entity just to know the usage of "process" My question is: Why the process is executed when the simulation just starts? I think the process wakes up when the signals in the ...
test-img

Hao Alessandro

vhdl

fpga

hdl

modelsim

asic

Votes: 0

Answers: 1

Latest Answer

All processes will execute at least once at time 0. A process with a sensitivity list is assumed to have a wait on <list> as the last statement in the process. You can read this in VHDL LRM Sect...
test-img

Tricky

Different Clock Domain VHDL

I'm making a custom hardware ARINC 429 Core. For now I have described the module in transmission (TX-FSM), according to the ARINC 429 standard and a FIFO in transmission from which it takes the data a...
test-img

KemKing

vhdl

hdl

fsm

arinc

Votes: 0

Answers: 1

Latest Answer

Run both FIFOs at the 2 MHz clk2M, and then generate a single cycle enable indication on TX_FIFO_rd when FIFO read data transfer is required. Thereby you can get the benefit from synchronous design, w...
test-img

Morten Zilmer

Posts

Questions

Blogs

Jobs