python (12.9k questions)

javascript (9.2k questions)

reactjs (4.7k questions)

java (4.2k questions)

java (4.2k questions)

c# (3.5k questions)

c# (3.5k questions)

html (3.3k questions)

Questions - iverilog

Are recursive functions in Verilog synthesizable?

Functions which do not contain any delay assignments are synthesizable, hence all synthesized functions are combinational in nature. Will the function still remain synthesizable if we have a recursive...
test-img

j_robot

recursion

verilog

iverilog

Votes: 0

Answers: 1

Latest Answer

Yes, recursive function can be synthesizable, but only if the depth of recursion can be determined at compile time. That usually means the arguments to each top-level call to the function are constant...
test-img

dave_59

I am trying use the output of a 16-bit encoder as to give input to the register (PIPO)

I am trying use the output of a 16-bit encoder as to give input to the register(PIPO). The 16-bit encoder will give 4-bit binary output; these 4-bit binary output will be given as input to the registe...
test-img

Sobebar Ali

verilog

test-bench

iverilog

Votes: 0

Answers: 2

Latest Answer

The error message tells you that you must not assign values to pipo_in in the testbench because you connected it to a module instance output. You also must not declare it as a reg; change it to a wir...
test-img

toolic

Posts

Questions

Blogs

Jobs