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No output data in sinc3 filter simulation
I have the following code for sinc3 digital filter in verilog:-
`timescale 1ns / 1ps
module dec256sinc24b
(input mclk1, /* used to clk filter */
input reset, /* used to reset filter */
input mdata1, ...

Pressing_Keys_24_7
Votes: 0
Answers: 2
How can I use display or monitor in verilog to check a register
I have 2 Modules. One is Register_File_Rf which is a file of 32 Registers I have created. I want to be able to see what every single register is storing.
Can I do this with $display or $monitor someho...
Xhulio Xhelilai
Votes: 0
Answers: 1
Testing multiple configurations of parameterizable modules in a Verilog testbench
Say I have a Verilog module that's parameterizable like the below example:
// Crunches numbers using lots of parallel cores
module number_cruncher
#(parameter NUMBER_OF_PARALLEL_CORES = 4)
(in...

John M
Votes: 0
Answers: 1
I am trying use the output of a 16-bit encoder as to give input to the register (PIPO)
I am trying use the output of a 16-bit encoder as to give input to the register(PIPO).
The 16-bit encoder will give 4-bit binary output; these 4-bit binary output will be given as input to the registe...
Sobebar Ali
Votes: 0
Answers: 2