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Questions about intel-fpga

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Questions - intel-fpga

I am getting error when check my systemverilog code in quartus II

I have this simple code checked with Quartus II. First, It gives me error 5000 iterations for loop limit then I try to change verilog constant loop limit variable in settings and now it is giving me t...
test-img

Dang Nhat

hardware

modelsim

quartus

intel-fpga

synthesis

Votes: 0

Answers: 1

Latest Answer

There a coding issue and maybe a resource utilization issue. The coding issue: The code infers block ram, and is attempting initialize/reset it. In general you can't reset block rams using a single in...
test-img

Mikef

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