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Questions - quartus

I am getting error when check my systemverilog code in quartus II

I have this simple code checked with Quartus II. First, It gives me error 5000 iterations for loop limit then I try to change verilog constant loop limit variable in settings and now it is giving me t...
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Dang Nhat

hardware

modelsim

quartus

intel-fpga

synthesis

Votes: 0

Answers: 1

Latest Answer

There a coding issue and maybe a resource utilization issue. The coding issue: The code infers block ram, and is attempting initialize/reset it. In general you can't reset block rams using a single in...
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Mikef

Changing triggering edge depending on clock polarity signal

I'm trying to implement some logic that is either triggered on a rising or falling edge of the same clock, depending on a clock polarity signal. I tried the following but got an error message in Quart...
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tobiashellbusch

vhdl

clock

edges

quartus

Votes: 0

Answers: 1

Latest Answer

Edit: I misunderstood the question. The below only applies if pol is a constant: Try the oldschool way of writing this, with separate event attribute and level: if clk'event and clk = pol then -- lo...
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blueshift

Verilog HDL syntax error at practice.v(7) near text "or"; expecting ")"

I have changed the setting to the same name as the module. There are no other Verilog files in the folder where this file is stored. I don't know what is wrong with the grammar. module test(A,B,F); in...
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周志桓

syntax-error

verilog

quartus

Votes: 0

Answers: 2

Latest Answer

or is a legal keyword in Verilog, but it can not be used in that context. It can be used as a built-in primitive OR gate, or in a sensitivity list. You likely want it to behave as the logical OR oper...
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toolic

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